Charge coupled EEPROM device and corresponding method of operation

ABSTRACT

This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate and electrically isolated therefrom; a plurality of wordlines, each of the gate structures being connected to one of the wordlines and a group of the gate structures being connected to a common wordline; and a plurality of active regions, each of the active regions being individually connectable to at least one of the gate structures.

CLAIM FOR PRIORITY

This is a national stage application of PCT/EP01/07542, filed Jul. 2,2001.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device and acorresponding method of operation.

BACKGROUND OF THE INVENTION

S. K. Lahiri: MNOS/Floating-Gate Charge Coupled Devices for High DensityEEPROMs: A New Concept, Physics of Semiconductor Devices, V. Kumar andS. K. Agarwal (eds.), Narosa Publishing House, New Delhi, India, 1998,pages 951–956, the basic idea of CCD EEPROMS is known. Particularly,this conference paper discloses the general idea to arrange EEPROM gatestructures each having a floating and a control (CCD) gate above asubstrate in rows separated by rails of active areas or injectorsprovided in said substrate. However, S. K. Lahiri fails to disclose asuitable memory address scheme for such a CCD EEPROM taking intoconsideration a dynamic clocking. Moreover, this document also fails todisclose appropriate cells layouts and operation modi.

For example, CCD devices are known from W. S. Boyle, G. E. Smith: ChargeCoupled Semiconductor Devices. The Bell System Technical Journal.American Telephone and Telegraph Company: New York, April 1970. Pages587–593; Rudolf Müller: Bauelemente der Halbleiter-Elektronik. SpringerVerlag: Berlin, Heidelberg, New York, London, Paris, Tokyo 1987. Seiten192–195; Kurt Hoffmann: VLSI-Entwurf. Modelle und Schaltungen.Oldenbourg Verlag: München, Wien 1996. Seiten 296–297; and Lev I.Berger: Semiconductor Materials. CRC-Press: 1997. Page 445.

EEPROM devices are generally well known in the state of the art. EEPROMcells are used to store information, which should be still accessibleafter switching the power supply off and on again, while being able tomodify the stored information multiple times by pure electrical means.EEPROM cells usually have source and drain contacts forming a MOStransistor. Information is read out by measuring the attributes of theoutput characteristic, which is dependent of the information stored in agate structure having floating and control gate.

The overall transfer characteristic (programming conditions to readcurrent) is highly nonlinear and strong dependent on several sideeffects and production fluctuations. I.e. the Fowler Nordheim tunnelingcurrent is more than exponentially dependent on the electric fieldacross the oxide. So the programming voltage and the oxide thicknesshave severe influence on the programming process. Thus, these parametersmust be adjusted with high precision. These accuracy problems limit themultilevel ability of known cell concepts to 2 bits per cell.

Fast cells are critical and must be handled with complex algorithms.Usually, only cells of a single wordline can be programmed at the sametime. During sensing, there is a static current consumption through Sand D of the MOS transistor. During parallel programming of cells in thetest phase, there is a static current due to the gate induced drainleakage, which must be supplied by a charge pump. This current drivingpump is area consuming.

Using drain and source contacts, the cell area of typical cells inembedded EEPROM modules results in 22*F² to 70*F². The world record forcells with drain and source contacts is 8.8*F².

Nowadays new applications for non-volatile memories are borne, one ofthat is the possibility to store photos or music in solid state device.In this kind of application is required a sequential data access to thememory.

SUMMARY OF THE INVENTION

The present invention provide an improved semiconductor memory deviceand a corresponding method of operation providing sequential dataaccess.

One embodiment of the present invention combines the charge shifting,receiving or providing (from now on denoted only by shifting) abilityand the possibility to store charge non-volatile in an oxide or on afloating gate (EEPROM) or a similar structure. The device or memorycells according to the invention will therefore be called charge coupledEEPROM cells or CC-EEPROM cells herein below.

In fact, by combining CCD and EEPROM technologies, it is possible toincrease the density of the memory and—at the same time—to build anon-volatile memory that is sequentially addressable itself and evenusable as a volatile memory.

CCD technique is known to operate with 8 bit resolution. In combinationwith the linear transfer characteristic of the charge coupled EEPROM andthe self limiting programming, this should provide deep multilevelability. Fast cells do not have any influence on the programmingprocess, because the programming stops, when all charge carrierstunneled to the floating gate. It is possible, to shift charge carriersinto the cell area and to program a huge number of wordlines inparallel. This cuts the programming time of some order of magnitude.There is no static current consumption during read. Minimum size cells(4F²) are possible, because the cell does not have drain or sourcecontacts. Reduction of logic in the bitline and wordline section resultin less chip area. There is an additional volatile memory functionality(i.e. using the same technology, it is also possible to implement highdensity memory buffer).

According to a preferred embodiment, a plurality of wordlines isprovided and a respective group of the gate structures being connectedto a respective wordline.

According to another preferred embodiment, the plurality of gatestructures for storing charge in a non-volatile manner is arranged inrows and columns.

According to another preferred embodiment, each row has an associatedfirst active region located at a first end of the row.

According to another preferred embodiment, each row has an associatedsecond active region located at a second end of the row.

According to another preferred embodiment, the wordlines are locatedabove the columns.

According to another preferred embodiment, between each of the activeregions and the at least one of the gate structures a gate structure forstoring charge in a volatile manner is arranged.

According to another preferred embodiment, a voltage generation devicefor applying individual voltages between the wordlines and the activeregions such that charge may be programmed, read, shifted, and erasedfrom the gate structures is provided.

According to another preferred embodiment, the substrate includes a bodycontact which is connected to the voltage generation device for applyingindividual voltages between the wordlines, the active regions and thesubstrate.

According to another preferred embodiment, the doping of the substrateis non-uniformly under the gate structures on the one hand and under aspacing between two of the gate structures of the other.

According to another preferred embodiment, a sense amplifier connectedto the active regions.

According to another preferred embodiment, a gate for separating the atleast one active region from the gate structures to selectively connectthe at least one active region to the gate structures for programming orreading said gate structures is provided.

According to another preferred embodiment, a programming of a gatestructure is arranged by supplying it with a programming voltage and bysupplying the other gate structures of the corresponding row with aselect voltage which is greater than the programming voltage.

According to another preferred embodiment, a programming of a gatestructure is arranged by supplying it with a programming voltage and bysupplying the gate structures of the corresponding row lying between thegate structure and the active region with a select voltage which isgreater than the programming voltage.

According to another preferred embodiment, a programming of a gatestructure is arranged by adjusting a charge quantity to be programmedunder one of the gate structures; shifting the charge quantity to beprogrammed from said one of said gate structures to another one of thegate structures; and programming said charge quantity to the another oneof the gate structures.

According to another preferred embodiment, a programming of a gatestructure is arranged by adjusting a charge quantity to be programmedbeneath a gate structure to be programmed; and programming the chargequantity to the gate structure.

According to another preferred embodiment, a reading of a gate structureis arranged by supplying it with a read voltage and by supplying theother gate structures of the corresponding row with a select voltagewhich is greater than said read voltage such that there is a staticcurrent flow between a first and second active region connected to theends of the row; and by sensing the static current flow.

According to another preferred embodiment, a read adjusting of a gatestructure is arranged by adjusting a charge quantity to be read underone of the gate structures by supplying it with a read adjust voltageand by supplying the gate structures of the corresponding row lyingbetween the gate structure and the active region with a select voltagewhich is greater than the read adjust voltage.

According to another preferred embodiment, a reading of a gate structureis arranged by said charge quantity to be read being shifted from theone of the gate structures to one of the active regions and sensed by asense amplifier connected thereto.

According to another preferred embodiment, an erase operation isperformed by applying an erase voltage across at least one of the gatestructures and said substrate.

According to another preferred embodiment, a multilevel programming ofthe gate structures is performed.

According to another preferred embodiment, a block programming isperformed by adjusting a respective programming charge beneath aplurality of the gate structures to be programmed and by simultaneouslyprogramming the plurality of the gate structures by applying aprogramming voltage.

According to another preferred embodiment, the semiconductor memorydevice according to the invention is used as a volatile memory.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are illustrated in the accompanyingdrawings and described in detail in the following.

In the Figures:

FIG. 1 shows a CC-EEPROM cell arrangement according to an embodiment ofthe invention.

FIG. 2 shows the erase mode for a specific gate structure of theCC-EEPROM cell arrangement according to the embodiment of the invention.

FIG. 3 shows the channel hot electron programming mode for a specificgate structure of the CC-EEPROM cell arrangement according to theembodiment of the invention.

FIG. 4 shows the Fowler Nordheim programming mode for a specific gatestructure of the CC-EEPROM cell arrangement according to the embodimentof the invention.

FIGS. 5 a,b show the adjust charge mode for programming a limited chargefor a specific gate structure of the CC-EEPROM cell arrangementaccording to the embodiment of the invention.

FIGS. 6 a–c show the charge shifting mode for shifting a limited chargefor a specific gate structure of the CC-EEPROM cell arrangementaccording to the embodiment of the invention.

FIG. 7 shows the Fowler Nordheim programming mode for programming alimited charge for a specific gate structure of the CC-EEPROM cellarrangement according to the embodiment of the invention.

FIG. 8 shows the NAND reading mode for a specific gate structure of theCC-EEPROM cell arrangement according to the embodiment of the invention.

FIGS. 9 a,b show the adjust charge mode for reading a limited charge fora specific gate structure of the CC-EEPROM cell arrangement according tothe embodiment of the invention.

FIGS. 10 a–c show the charge sink and sense amplifier for a specificgate structure of the CC-EEPROM cell arrangement according to theembodiment of the invention.

FIG. 11 shows a possible two-dimensional CC-EEPROM cell arrangementaccording to an embodiment of the invention.

Throughout the figures the same reference numbers indicate the same orfunctionally equivalent means. It should be noted that the individualfigures for explaining specific modes of operation do not include alldetails, but just the details needed for explaining the respective mode.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a CC-EEPROM cell arrangement according to a embodiment ofthe invention in a schematic representation.

In FIG. 1, reference sign 1 denotes a p-type semiconductor substrate,e.g. a silicon substrate, having an n⁺-type source and drain region 10and 20, respectively, and having a p⁺-type body contact 30.

Between the n⁺-type source and drain regions 10, 20 there is a pluralityof aligned gate structures. The gate structures include floating gatesFG1, FG2, . . . , FGn−1, and FGn above the substrate surface andelectrically isolated therefrom. Moreover, each of the floating gatesFG1, FG2, . . . , FGn−1, and FGn has a corresponding control gate CG1,CG2, . . . , CGn−1, CGn which is electrically isolated therefrom. Thusthe gate structures are similar to the gate structure of an EEPROM,however, here a plurality of gate structures each consisting of afloating and control gate pair is aligned with preferably equidistantspacing.

S, G1, G2, . . . , Gn−1, Gn, D, B denote respective contacts of thecorresponding source, drain, bulk, and gate regions. Only schematicallyshown in FIG. 1 is a voltage generation device 100 for applyingindividual voltages between said gate structures CG1, FG1; . . . ; CGn,FGn and said active regions 10, 20 and body contact 30 such that chargemay be programmed, read, shifted, and erased from said gate structuresCG1, FG1; . . . ; CGn, FGn. The voltage generation device 100 isconnected to the respective contacts of the corresponding source, drain,bulk, and gate regions S, G1, G2, . . . , Gn−1, Gn, D, B. The associatedfunctions will be described later.

The direction SD pointing from the source region 10 to the drain region20 along the gate structures is called shifting direction. In thisshifting direction SD, the intermediate cell gate structures are notflanked by a heavy source/drain doping like in normal EEPROM cells orMOS transistors—otherwise the charge isolating and conserving capabilityfor the adjusted charge to be described later would vanish. However, toa certain limit, light source/drain doping may be acceptable.

The CC-EEPROM cell arrangement of FIG. 1 is arranged in a way, thatcharge can be shifted from one gate structure to another, i.e. CCD like.The cell arrangement contains a minimum of one non-volatile cell. Gatestructures of this arrangement need not all to be non-volatile cells(e.g. there may be gates just for shifting, gates just supplyingvolatile memory or gates next to a heavy source or drain doping) or neednot all to be used for non-volatile storing (e.g. there may be dummycells or gates next to a heavy source or drain doping). The gatealignment needs not to have straight line characteristic, but meander,tree, parallel, . . . structures are also possible.

The arrangement normally has a minimum of one contacted or uncontactedsource/drain doping, which can act as a charge source or sink. Thisdoping can be located on the beginning or end (edge) of the arrangement.There might be a bulk contact. Bulk can but needs not to be isolatedfrom the substrate by any means (junction, oxide, insulator). A minimumcell area is feasible due to the minimum number of drain and sourcecontacts.

Doping is somehow a subject for trade off (see below) and can be donenon-uniformly or differently under the tunnel oxide on the one hand andunder the spacing between two gates of the other. However, also uniformdoping is possible.

For shifting inversion charge from one gate structure to the other, thedepletion regions, which are induced by these gates, must touchlaterally. This is achieved at relatively low or medium voltages, whenthe effective doping between these gates is low. Thus, a low intrinsicbulk doping or a contra doping is preferred.

Programming voltage is shared by the inter poly oxide (between floatingand control gate), the tunnel oxide (both effects known from normalEEPROM cells) and an unwanted, extending depletion region under thecell.

In order to achieve the electrical field in the tunnel oxide, needed forFowler Nordheim tunneling, at a minimum programming voltage, thisdepletion region can be limited by a heavy doping beneath the tunneloxide, eventually spaced to the semiconductor surface.

Heavy doping is in contradiction to the need mentioned above regardingcharge shifting. Therefore, the above mentioned trade-off should befound in practice. In any case, low doping is needed only at thesurface.

Generation and recombination limit the available time after start ofadjusting charge quantities to completion of reading or programming. Theburied CCD approach known from R. H. Walden, R. H. Krambeck, R. J.Strain, J. McKenna, N. L. Schryer, G. E. Smith: The Buried ChannelCharge Coupled Devices. The Bell System Technical Journal. AmericanTelephone and Telegraph Company: New York, September 1972. Pages1635–1640; and D. J. Burt: Basic Operation of the Charge Coupled Device.Proc. Int. Conf. Technol. Applic. CCD. Edinburgh University: Edinburgh1974, Pages 1–12, which is used to cope with the high generation andrecombination at the semiconductor/oxide interface, increases the readimmunity and requires increased program voltage.

FIG. 2 shows the erase mode for a specific single gate structure CG1,FG1 of the CC-EEPROM cell arrangement according to the embodiment of theinvention.

In order to explain that this embodiment of the invention is compatiblewith normal non-volatile memory operation, here is showed, how to eraseone cell having control gate CG1 and floating gate FG1 or all inparallel, applying appropriate bias and using the well known FowlerNordheim tunneling.

Erasing is done by applying an electrical field to the tunnel oxide inthe orientation, that majority charge carriers, here holes (+), areaccumulating on the semiconductor surface in an accumulation region AC.Thereby, electrons (−) stored in the floating gate FG1 may be extracted.Therefore, an erase voltage V_(er) is applied across a minimum of oneCCD cell line bulk on the one hand and a minimum or one cell controlgate on the other. This erase voltage V_(er) of typically 16–18 Vphysically adds to the source-bulk-voltage V_(SB) of typically >−0,7 V.It should be mentioned that here and in the following description allvoltages are referred to the source voltage, however, this is just oneof several possibilities.

Erase is not self-limiting and cells behave differently, so one or moreread verify plus program cycles may complete the erase step.

Next, programming of the CC-EEPROM cells will be explained. In knownmemory devices, programming was always performed with unlimited chargefor a predetermined time period. However, according to this embodimentprogramming can either be done with unlimited charge or with limitedcharge.

Particularly, programming with an unlimited charge source provides arandom access possibility.

Programming voltage and/or programming time adjust the amount of charge,which is tunneling from the inversion layer through the tunnel oxide tothe floating gate (Fowler Nordheim tunneling) or is injected into thetunnel oxide (channel hot electron).

FIG. 3 shows the channel hot electron programming mode for a specificgate structure of the CC-EEPROM cell arrangement according to theembodiment of the invention.

This structure is operated somehow similar to a NAND CHE (channel hotelectron) EEPROM. The source/drain doping inbetween two cells isfunctionally substituted by supplying an appropriate V_(sel) to allcells, which should not be programmed, so that the gaps between cellshave a continuous inversion layer INV. The cell having the gatestructure FG3, CG3 to be programmed is supplied with a programmingvoltage V_(pr) which is smaller than V_(sel), while V_(sel) is greaterthan V_(DS). These voltages add to the source-bulk-voltage V_(SB).

By supplying these voltages, a charge density CDE is created below thegate structure FG3, CG3. At the location where this charge density CDEis nearly zero, a channel hot electron region CHE is created from wherehot electrons can enter into the floating gate FG3.

It should be noted that when using channel hot electron programming, itis also possible to use a SONOS gate structure leaving out the floatinggate, as described in Boaz Eitan, Paolo Pavan, Ilar Bloom, Efraim Aloni,Aviv Frommer, David Finzi: NROM: A Novel Localized Trapping, 2-BitNonvolatile Memory Cell. IEEE Electron Device Letters, Vol. 21, No. 11.IEEE: November 2000. Pages 543–545.

FIG. 4 shows the Fowler Nordheim programming mode for a specific gatestructure of the CC-EEPROM cell arrangement according to the embodimentof the invention with unlimited charge source.

An inversion layer INV is built up from the source 10 to the cell havingthe gate structure FG3, CG3 which should be programmed. This can be doneby selecting and deselecting other cells in an appropriate manner or byanother special gate structure, which is placed near by every cell (e.g.in the third dimension).

Here, the select voltage V_(sel) is applied to the two left hand cellsand a deselect voltage V_(desel) is applied to the right hand neighbourcell. The cell having the gate structure FG3, CG3 to be programmed issupplied with a programming voltage V′_(pr) which is greater than V_(pr)in the case of channel hot electron programming. Fowler Nordheimprogramming mode has the advantage that it is current saving incomparison to channel hot electron programming, because no current flowexists between source and drain 10, 20.

Next, programming with a limited charge will be explained. Programmingwith a limited charge source is done in three steps: adjusting chargequantity, shifting the charge to the cell to be programmed and finallyprogramming, which means that this charge is tunneled to the floatingarea of the cell to be programmed.

Adjusting and shifting charge can be done in parallel, so that a hugefraction of the sector can be filled with this information carryingcharge quantities, which can finally be programmed in parallel (burstprogramming). In other words, having a two-dimensional array of CCEEPROM cells, first the information of all cells may be shifted underthe array, and then all the information may be programmed in a singlestep. Because programming is time consuming (several milliseconds forFowler Nordheim tunneling), this parallel programming dramaticallyspeeds up the memory filling with a continuous data stream (burst).

There is no need for a special page buffer, which results in a smallerchip area due to the reduced logic in the bitline section.

The programming of a cell ends automatically, when all charge beneaththe tunnel oxide is tunneled to the floating gate. A self-limitingprogramming is achieved, supplying a multilevel ability, even in case offast cells.

FIGS. 5 a,b show the adjust charge mode for programming a limited chargefor a specific gate structure of the CC-EEPROM cell arrangementaccording to the embodiment of the invention.

Techniques for adjusting the charge quantity which will be programmedlater on are well known from charge coupled devices (CCD filters).

First, as illustrated in FIG. 5 a a continuous inversion layer INV isbuilt up from the source 10 to the adjusting gate structure CG2, FG2 byselecting the gate structure CG1, FG1 inbetween. Moreover, the righthand neighbor gate structure CG3, FG3 is deselected.

The amount of charge Q_(Ipr) is adjusted by the program adjust voltageV_(prad) which is linearly related by the following formula:Q _(Ipr) =−A _(ox)(C _(ox)″(V _(prad) −V _(FB)−2Φ_(F))−√{square rootover (2qε ₀ε_(Si) N _(A)(2Φ_(F) +V _(SB))))}  (0)which is valid in the case that the adjusting MOSFET does not have afloating gate. Here Φ_(F) is the Fermi potential, V_(FB) the flatbandvoltage, V_(SB) the source-bulk voltage, and the remaining terms areconstants. If the adjusting MOSFET has a floating gate, then formula 11below applies.

Then, with reference to FIG. 5 b this adjusted charge is separated fromthe source 10 by deselecting the gate structure CG1, FG1 between thesource 10 and the adjusting gate structure CG2, FG2.

Instead of adjusting the charge quantity by the V_(prad) voltage, thedesired charge amount could also be brought in via the source contact S(see FIG. 1) which would not be at a fixed potential in this case. Thecharge can also be delivered by a charge adjusting circuitry which isconnected to the source contact.

The cell having the gate structure CG1, FG1 next to the source 10 is adummy cell (no information storage is possible in limited chargeprogramming mode) and in principle needs not to have a floating gate.The next cell, to which V_(prad) is applied, could also be a dedicatedtransistor.

Adjusting can be done in parallel to reading another wordline asexplained later.

FIGS. 6 a–c show the charge shifting mode for shifting a limited chargefor a specific gate structure of the CC-EEPROM cell arrangementaccording to the embodiment of the invention.

Charge shifting from one cell to another is well known and vastlydocumented for charge coupled devices (CCD camera, CCD filter).

The easiest way to achieve this is to interconnect the control gate ofevery third cell. This results in only three wordlines, which must bedriven in an appropriate manner. So, a corresponding wordline sectionneeds less control logic and less driving units, resulting in a reducedchip area.

As shown in FIG. 6 a, the starting situation is identical with thesituation of FIG. 5 b. Additionally shown is the gate structure havingcontrol gate CG4 and floating gate FG4 which is also deselected.

Having regard to FIG. 6 b, the gate structure CG3, FG3 is then selectedby applying selection voltage V_(sel). As a consequence, inversion layerINV expands to the gate structure CG3, FG3.

Now, as shown in FIG. 6 c, the gate structure CG2, FG2 is deselected byapplying deselection voltage V_(desel). As a consequence, inversionlayer INV contracts to the gate structure CG3, FG3 which remainsselected.

By the above process sequence, the limited charge quantity is shiftedfrom one cell to the other.

FIG. 7 shows the Fowler Nordheim programming mode for programming alimited charge for a specific gate structure of the CC-EEPROM cellarrangement according to the embodiment of the invention.

Non-volatile programming is done by applying programming voltage V_(pr)to the control gates of cell having the gate structure CG3, FG3 whichshould be programmed, leaving the neighbor cells deselected.

The equation for the Fowler Nordheim tunneling current density accordingto Georg Tempel: Reprogrammable Silicon-based Non Volatile Memories.Infineon Technologies AG. CPD IPD RC IMEC: Leuven, Belgium 2001. Page1–29, reads:

$\begin{matrix}{J_{FG} = {\alpha\; E_{tox}^{2}ɛ^{\frac{\beta}{E_{tox}}}}} & (1) \\{E_{tox} = \frac{V_{FG} - V_{l}}{d_{tox}}} & (2) \\{\alpha = {\frac{m}{m*}\frac{q^{3}}{8\;\pi\; h\;\Phi_{b}}}} & (3) \\{\beta = {4\sqrt{2\; m*}\frac{2\pi}{3{hq}}\Phi_{b}^{\frac{3}{2}}}} & (4)\end{matrix}$with

h 6.6 · 10⁻³⁴ Js Planck's constant Φ_(b) 3.2 eV energy barrier (Si—SiO₂)at injecting interface q 1.6 · 10⁻¹⁹ C charge of single electron m 9.1 ·10⁻³¹ kg mass of free electron m* 0.42 m effective mass of (SiO₂)electron in band gapand was originally derived under the assumption that the conduction bandis filled with charge carriers.

However, when using the CCD principle for shifting charge beneath thefloating gate in order to program, this charge is limited and steadilydecreasing when charge carriers tunnel onto the floating gate duringprogramming phase. Therefore it is assumed that the tunnelingprobability for each charge carrier is identical. This results in anapproximately exponential tunneling current drop by time (neglectingelectric field reduction due to charging of the floating gate).

Thus, using the CCD principle, a single programming procedure willapproximately take 3 times longer than usually as rule of thumb.However, using burst programming, there will be still an enormous timesaving compared to conventional programming time.

The limited charge programming procedure may also be done in two steps,namely first program adjust beneath the cell to be programmed (like readadjust in FIG. 5) and secondly program the charge to the floating gateas mentioned above.

Next, reading of the cells will be explained. There are two differentpossible reading modes, the NAND mode and the CCD mode.

The NAND mode reading provides a random access. The situation of readingin NAND mode is very similar to channel hot electron programming. Onlythe applied read voltage V_(read) is different.

FIG. 8 shows the NAND reading mode for a specific gate structure of theCC-EEPROM cell arrangement according to the embodiment of the invention.

As a consequence of the applied voltages, namely V_(sel) to the cellsnot to be read and V_(read) to the cell to be read, there is a staticcurrent flow I_(s) which may be sensed by a sense amplifier SA.

In analogy with the CCD programming mode, the CCD reading mode consistsof three operation procedures: adjusting read charge, shifting chargetowards the output and sensing the charge. There is no static currentconsumption. As a consequence of the shifting procedure, there is only aburst reading without a random access possibility.

Here, the charge density CDE in the reading region RR depends on theinformation stored in the cell.

FIGS. 9 a,b show the adjust charge mode for reading a specific gatestructure of the CC-EEPROM cell arrangement according to the embodimentof the invention.

Adjusting the reading charge is a preparation phase for the reading. Itcan be done in parallel to reading another wordline.

According to FIG. 9 a, an inversion layer INV is built up from thesource 10 to the cell having gate structure CG3, FG3 which is to beprepared. This can be done by selecting and deselecting other cells inan appropriate manner or by another special gate structure, which isplaced near by every cell.

Here, the select voltage V_(sel) is applied to the two left hand cellsand a deselect voltage V_(desel) is applied to the right hand neighbourcell. The cell having the gate structure FG3, CG3 to be prepared issupplied with a read adjust voltage V_(readad) such that the charge ofthe inversion layer INV under the cell is a function of the charge onthe floating gate. V_(sel) is greater than V_(readad), so that thedepletion region under the shifting cell is independent of the storedcharge on the floating gate of other cells.

According to FIG. 9 b, the inversion layer charge is finally separatedfrom the continuous inversion layer INV to the source 10 by deselectingthe neighbour gate having the gate structure CG2, FG2.

After adjusting the charge for reading, the charge must be shiftedtowards the output node by the shifting mode explained above with regardto FIG. 6.

FIGS. 10 a–c show the charge sink and sense amplifier for a specificgate structure of the CC-EEPROM cell arrangement according to theembodiment of the invention.

Sensing is done in parallel to the charge shifting. The sense amplifierSA is connected to the output node, which acts as a charge sink for theshifted charge. As the output node, either the drain 20 or the source 10can be used. The cell next to the drain 10 is a dummy cell and needs notto have a floating gate (i.e. floating gate may be omitted or floatinggate and control gate may be shorted).

Sensing is well known and documented for charge coupled devices such asCCD camera, CCD filter etc. These known sensing devices proved to becapable sensing at an 8 bit resolution, and facilitate deep multilevelsensing ability for CC-EEPROM cells according to this embodiment.

According to FIG. 10 a, the cell having gate structure CG2, FG2 isdeselected, and the cells having gate structures CG3, FG3 and CG4, FG4are selected. So, the charge to be read is shifted to the drain 20 fromthe gate structure FG3, CG3.

According to FIG. 10 b, the cell having gate structure CG4, FG4 isselected, and the cells having gate structures CG2, FG2 and CG3, FG3 aredeselected. So, the charge to be read is isolated at the drain 20 fromthe gate structure FG3, CG3.

According to FIG. 10 c, the cell having gate structure CG2, FG2 isselected, and the cells having gate structures CG3, FG3 and CG4, FG4 aredeselected. So, new charge to be read coming from gate structure CG1,FG1 (not shown in FIG. 10 c) is transferred to the gate structure FG2,CG2.

Next, the read transfer characteristic will be evaluated. Heretofore,the following physical quantities must be considered:

C_(tox) tunnel oxide capacitance C_(D,abs) absolute depletion regioncapacitance C_(sp) inter poly capacitance C_(fr) fringing capacitanceQ_(A) ambient charge Q_(CG) control gate charge Q_(D) depletion regioncharge Q_(FG) floating gate charge Q_(I) inversion layer charge V_(A)ambient voltage V_(CG) control gate voltage V_(FG) floating gate voltageV_(I) inversion layer voltage V_(b) bulk voltage V_(CG) = V_(adjust) −V_(FB) + V_(b) + V_(SB) control gate potential (where Vadjust is therespective adjust voltage) V_(FB) = −kT/q ln(N_(A) N_(D,CG)/n_(i) ²)flat band voltage V_(I) = 2 Φ_(F) + V_(SB) + V_(b) inversion layerpotential Φ_(F) = kT/q ln(N_(A)/n_(i)) Fermi potential

In order to be neutral outside of the structure, the sum of all chargesmust be zero.Q _(FG) +Q _(CG) +Q _(A) +Q _(I) +Q _(D)=0  (5)

The equations for the oxide capacitances areQ _(CG) =C _(ip)(V _(CG) −V _(FG))  (6)Q _(A) =C _(fr)(V _(A) −V _(FG))  (7)Q _(I) +Q _(D) =C _(tox)(V _(I) −V _(FG))  (8)

Equation (8) is rewritten'to be

$\;\begin{matrix}{V_{FG} = {V_{I} - \frac{Q_{I} + Q_{D}}{C_{tox}}}} & (9)\end{matrix}$

The equation for the depletion region capacitance isQ _(D)=√{square root over (2qε ₀ε_(Si) N _(A)(V ₁ −V _(b)))}*A_(tox)  (10)where C_(D,abs) denotes an absolute capacitance. Equations (6), (7), (9)and (10) inserted in equation (5) result inQ _(I) =−γQ _(FG) +Q ₀  (11)

$\begin{matrix}{\gamma = \frac{C_{tox}}{C_{tox} + C_{ip} + C_{fr}}} & (12) \\{with} & \; \\\begin{matrix}{Q_{0} = {{\sqrt{2q\; ɛ_{0}ɛ_{Si}{N_{A}( {{2\Phi_{F}} - V_{SB}} )}}*A_{tox}} -}} \\{{\gamma\;{C_{ip}( {V_{adjust} - V_{FB} - {2\Phi_{F}}} )}} -} \\{\gamma\;{C_{fr}( {V_{A} - {2\Phi_{F}} - V_{SB} - V_{b}} )}}\end{matrix} & (13)\end{matrix}$

This equation shows that the inversion layer charge is linear dependentof the floating gate charge. This clearly reveals the multilevel abilityof of the CC-EEPROM cell arrangement according to the embodiment of theinvention.

A volatile memory functionality of unused memory sectors is achieved bythe following steps: adjusting charge quantity, shifting this chargeunder the desired gate structure, storage phase, shifting the charge tothe output node and finally sensing the charge. This storage mode haseither a first in first out or a first in last out behavior, namelydependent on what the output node is, i.e. source or drain. It can beused e.g. for storing the data to be programmed in another sector inorder to realize a target programming algorithm.

FIG. 11 shows a possible two-dimensional top view of a CC-EEPROM cellarrangement according to an embodiment of the invention.

In FIG. 11, reference signs WL1–W15 denote five different wordlinesarranged in parallel and equidistantly. S1–S4 and D1–D4 denoterespective source and drain regions.

Between source S1 and drain D1, there are five gate structures eachconsisting of a floating gate and a control gate, the control gatesbeing connected to the wordlines WL1–WL5 at contacts K11, K21, K31, K41,K51.

Between source S2 and drain D2, there are five gate structures eachconsisting of a floating gate and a control gate, the control gatesbeing connected to the wordlines WL1–WL5 at contacts K12, K22, K32, K42,K52.

Between source S3 and drain D3, there are five gate structures eachconsisting of a floating gate and a control gate, the control gatesbeing connected to the wordlines WL1–WL5 at contacts K13, K23, K33, K43,K53.

Between source S4 and drain D4, there are five gate structures eachconsisting of a floating gate and a control gate, the control gatesbeing connected to the wordlines WL1–WL5 at contacts K14, K24, K34, K44,K54.

Not shown in FIG. 11 for simplification are isolation structures betweenshifting channels.

By sequentially applying appropriate voltages to the wordlines WL1–WL5and to the source and drain regions S1–S4 and D1–D4, information can beshifted in parallel along the shifting direction SD under the gatestructures of wordline WL2 and WL4 and simultaneously be programmed witha single programming burst. In analogy reading may be performed byshifting out the information in parallel along the shifting direction SDto the drains D1–D4.

In order to prove the most critical aspects to work—charge transfer,charge isolation and applying programming voltage—a device simulationwas done. This simulation showed that it is possible to build up astructure, which can shift charge, isolate it and apply a programmingvoltage while the quantity of isolated charge is only hardly altered byleakage current and thermal generation.

Although the present invention has been described with regard tospecific embodiments, it is not limited thereto, but may be modified inmany ways.

Particularly, CC-EEPROM cells or arrangements can also be mixed withother, well known EEPROM cells or cell elements in order to bring intheir functionality.

Just for generality, it is possible to add some more gates or dopingprofiles to the arrangement mentioned above, which are addedperpendicular to (or better: not in the same direction of) the shiftingdirection SD. These means can provide additional functionality.

The floating gates of a CC-EEPROM cell can be routed out of the cellshifting area and can be connected to other structures (gate, flankeddoping, transistor, tunnel oxide, . . . ), in order to provideadditional functionality or to combine known NVM (non-volatile memory)principles (channel hot electron, Fowler Nordheim tunneling, reading viaMOSFET, . . . ) or charge shifting principles (CCD) with the CC-EEPROMcell principle. So, a minimum of one CCD principle is used in order toerase, program, read non-volatile memory.

1. A semiconductor memory device, comprising: a semiconductor substratehaving a first conductivity; a chain of gate structures includingfloating gates for storing charge in a non-volatile manner regularlyarranged in above the surface of the semiconductor substrate andelectrically isolated therefrom; and at least one active region having asecond conductivity, wherein each of the at least one active regions isindividually configured to be connected to at least one of the gatestructures within the chain of gate structures by interconnecting thegate structures lying between the at least one gate structure and theactive region such that charge is configured to be programmed, read,shifted, and erased with respect to the gate structure, and whereinbetween each of the at least one active regions and the at least one ofthe gate structures, a gate structure for storing charge in a volatilemanner is arranged.
 2. The semiconductor memory device according toclaim 1, wherein a plurality of word lines is provided and a respectivegroup of the gate structures being connected to a respective word line.3. The semiconductor memory device according to claim 1, wherein theplurality of gate structures for storing charge in a non-volatile manneris arranged in rows and columns.
 4. The semiconductor memory deviceaccording to claim 3, wherein each row has an associated first activeregion located at a first end of the row.
 5. The semiconductor memorydevice according to claim 4, wherein each row has an associated secondactive region located at a second end of the row.
 6. The semiconductormemory device according to claim 2, wherein the wordlines are locatedabove the columns.
 7. The semiconductor memory device according to claim1, further comprising a voltage generation device for applyingindividual voltages between the wordlines and the active regions suchthat charge may be programmed, read, shifted, and erased from the gatestructures.
 8. The semiconductor memory device according claim 7,wherein the substrate includes a body contact which is connected to thevoltage generation device for applying individual voltages between thewordlines the active regions and the substrate.
 9. The semiconductormemory device according to claim 1, wherein doping of the substrate isnon-uniformly under the gate structures and under a spacing between twoof the gate structures.
 10. The semiconductor memory device according toclaim 1, further comprising a sense amplifier connected to the activeregions.
 11. The semiconductor memory device according to claim 1,further comprising a gate for separating the at least one active regionfrom the gate structures to selectively connect the at least one activeregion to the gate structures for programming or reading the gatestructures.
 12. A method of operating a semiconductor memory device, thedevice having a semiconductor substrate having a first conductivity; achain of gate structures including floating gates for storing charge ina non-volatile manner regularly arranged in above the surface of thesemiconductor substrate and electrically isolated therefrom; and atleast one active region having a second conductivity, wherein each ofthe at least one active regions is individually configured to beconnected to at least one of the gate structures within the chain ofgate structures by interconnecting the gate structures lying between theat least one gate structure and the active region such that charge isconfigured to be programmed, read, shifted and erased with respect tothe gate structure, and the plurality of gate structures for storingcharge in a non-volatile manner is arranged in rows and columns, themethod comprising: programming a gate structure by supplying its controlgate with a programming voltage and by supplying the other gatestructures of the corresponding row with a select voltage which isgreater than the programming voltage.